Optimizing MOS Transistor Mismatch
نویسندگان
چکیده
An investigation of MOS transistor mismatch is undertaken and a methodology is developed for optimizing mismatch without increasing layout area. Dramatic improvements of up to 300% in matching can be realized by selecting the optimum W=L ratio without changing the overall WL area product. The theoretical basis for the obtainable improvements is fully described and an expression is derived and verified by experiment to predict the W=L ratio which gives optimum matching.
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